Electrostatic discharge (ESD) is the spontaneous and rapid transfer of electrostatic charge between two objects having different electrostatic potentials. Familiar examples of ESD range from the relatively harmless, such as the shock one might receive after shuffling across a carpet and touching a doorknob, to the extreme, such as a lightning bolt. In the world of electronic devices and in particular integrated circuits (ICs), ESD is a very significant problem. The heat generated by ESD can cause metal to open due to melting, junction electrothermal shorts, oxide rupture or other serious damage to the IC components. Susceptibility to ESD increases with the shrinking size of technology, and components directly connected to the I/O pads are particularly vulnerable.
In view of the above, ESD protection devices are present in every modern IC. They are typically placed in parallel with the circuitry to be protected so that large transient currents caused by ESD events can be safely shunted away. Such devices are sometimes referred to in the industry as ESD “clamps” as the node voltage is clamped to a safe level.
N-type metal-oxide semiconductor field effect transistors (MOSFETs) (commonly referred to as NMOSs or NFETs) are commonly used as ESD protection devices in ICs. Typically, the drain of the NMOS is connected to the pad and the gate (usually grounded) is coupled to the source. As depicted in FIG. 1, as the drain voltage rises during an ESD transient, reverse bias current also increases (region 10) until the trigger voltage Vt of the parasitic bipolar transistor (comprised of the drain, body and source) is reached. At the trigger voltage, avalanche occurs and the I-V characteristic enters what is known in the industry as “snapback” (region 12). Without some provision for conduction uniformity, the current would increase virtually unchecked until burn-out occurred (dashed line 14). However, if conduction uniformity is provided, a safe current limit at high ESD voltages can be maintained (region 16) and the ESD current can be safely shunted away from the IC circuitry.
Conduction uniformity is achieved by adding ballasting resistance between the gate and drain of the NFET. FIG. 2 depicts a conventionally-ballasted NFET 20. NFET 20 includes drain 22 (N+ diffusion or implant region), gate (typically polysilicon) 24 and source 26. The drain diffusion 22 and the source diffusion 26 are typically salicided, and ballasting is achieved by extending the spacing Scgd between drain contacts 28 and gate 24, and inserting a salicide block mask 30. Insertion of block mask 30 causes the resistivity of the N+ diffusion or implant region to increase from about 7 Ω/square to about 100 Ω/square. To keep contact resistance low and ohmic, the drain contacts 28 should be directly coupled to the salicided diffusion region. Hence, an opening 32 is formed in block mask 30 to keep salicide in the region of drain contacts 28. An additional spacing Scsb is provided between block mask 30 and contacts 28 for this purpose.
Ballasting resistance serves several functions. First, it allows uniform snap-back triggering on the section or fingers of a MOSFET. Without a ballast resistance, one section may trigger ahead of others and become destroyed before other sections turn on. Ballast resistance raises the failure voltage of a section to the point where other sections can trigger before the first triggering section fails. Second, current and heat build-up in channel regions reaching the critical temperature is limited. The Critical temperature is the temperature at which the intrinsic carrier concentration or thermal generated carrier concentration exceeds the background carrier concentration.
One problem with prior art ESD protection devices such as NFET 20 is that the ballasting region is long and space consuming. For a conventional, unballasted NFET in a 0.15 μm process, for example, the spacing Scgd between the drain contacts and gate is about 0.15 μm. Where ballasting is employed, as in FIG. 2, the spacing Scgd increases dramatically to over 2 μm. This large gate-to-drain contact dimension not only increases layout area but also increases drain capacitance. To deal with heat generation at source contacts 34, the spacing Scp between poly gate 24 and source contacts 34 must also be quite large, and is typically in the range from 0.5 to 0.8 μm.
NFET 20 is susceptible to failure as a result of the formation of hot spots during snapback. Hot spots are a consequence of a second breakdown in which a region between the drain and source diffusion areas reaches a critical temperature wherein the charge carrier density is dominated by thermally generated carriers. The exponential relationship between carrier density and temperature and the resulting decrease in regional resistance with increasing temperature results in thermal “runaway”. A positive feedback mechanism exists between the regional temperature and electrical power. The process of rapid temperature increase results in the formation of a conductive filament 36 which being formed under gate 24 and ultimately melts the silicon thereby forming a permanent short circuit between drain 22 and source 26.
As seen in FIG. 2, the current conducting into filament 36 spreads out away from filament 36 and is able to flow in an expanding path 38 toward the drain contacts 28. The expanding flow pattern creates a small series resistance seen by the filament unless the resistivity of the ballast resistance region is large or the length of the ballast region is large. The inventor has realized that the series resistance seen by the conducting hot spot filament itself is a significant factor in inhibiting the conductive filament from reaching the melt temperature of silicon and is a greater factor in inhibiting permanent damage than the overall drain resistance per se.